In layout design of a semiconductor integrated circuit, a value of current flowing through power source wiring is calculated to determine a power source wiring width, and the determined power source wiring width is used for wiring a signal line of a functional block in a conventionally known technique (see, e.g., Japanese Laid-Open Patent Publication No. 2000-58653).
In layout design of a semiconductor integrated circuit, a value of current flowing through terminals of cells and a required line width of each of the terminals are calculated to determine a required line width of wiring, and the determined required line width of wiring is used for wiring in a conventionally known technique (see, e.g., Japanese Laid-Open Patent Publication No. H5-206276).
In layout design of a semiconductor integrated circuit, a constant proportional to a length of a cell array is defined for each block such that a decrease in the power source of the block does not exceed a standard value, whereby a line width of power source wiring is determined according to the constant in a conventionally known technique (see, e.g., Japanese Laid-Open Patent Publication No. S63-96939).
Nonetheless, to supply a power to an analog circuit, for example, an input/output circuit of the power source is disposed dedicated for the analog circuit and therefore, a problem arises in that the input/output circuits increase according to the number of the analog circuits.